In recent years, active matrix-type liquid crystal display devices including TFTs (thin film transistors) as switching elements have been known. Such a liquid crystal display device includes a liquid crystal panel having two insulating substrates opposed to each other. One substrate of the liquid crystal panel has gate bus lines (scanning signal lines) and source bus lines (video signal lines) provided thereon in a lattice pattern, while having the TFTs provided in the vicinities of intersections of the gate bus lines and the source bus lines. The TFTs each have a gate electrode branched from the gate bus line, a source electrode branched from the source bus line, and a drain electrode. The drain electrodes are connected to pixel electrodes arranged in a matrix on the substrate for image formation. The other substrate of the liquid crystal panel has an electrode (hereinafter, referred to as a “counter electrode”) provided thereon for applying voltage between a liquid crystal layer and the pixel electrodes via the liquid crystal layer, such that each pixel is formed by the pixel electrode, the counter electrode, and the liquid crystal layer. Note that such an area in which a single pixel is formed is referred to as a “pixel formation portion” for convenience. Voltage is applied to the pixel formation portion based on a video signal (data signal) received by the source electrode of the TFT from the source bus line when the gate electrode of each TFT receives an active scanning signal (gate signal) from the gate bus line. The pixel formation portion has formed therein a pixel capacitance. Voltage indicating a pixel value is held in the pixel capacitance.
Incidentally, liquid crystals have the property of deteriorating when DC voltage is continuously applied thereto. Therefore, in the case of liquid crystal display devices, AC voltage is applied to the liquid crystal layer. Application of the AC voltage to the liquid crystal layer is achieved by inverting the polarity of voltage being applied to each pixel formation portion every frame period, i.e., by inverting the polarity of source electrode voltage conforming with the potential of the counter electrode every frame period. Note that the voltage being applied to the pixel formation portion is referred to below as “pixel voltage”. As a technology for implementing the application of the AC voltage to the liquid crystal layer, a drive method is known in which the polarity of the pixel voltage is inverted every frame period, and polarities are also inverted within one frame period between adjacent pixels along the direction in which the gate bus lines extend and along the direction in which the source bus lines extend. Such a drive method is referred to as “dot-inversion drive”. FIG. 7 is a polarity diagram showing the polarities of pixel voltage being applied to pixel formation portions on a display screen during a given frame period in a liquid crystal display device employing the dot-inversion drive method. As shown in FIG. 7, the polarity of the pixel voltage is inverted between all adjacent pixels.
However, the conventional dot-inversion drive has such problems as increased power consumption and increased heat generation because the polarity of the pixel voltage is inverted every gate bus line. Accordingly, there has been proposed a drive method in which the polarity of the pixel voltage is inverted every two gate bus lines, and furthermore, the polarity inversion is also performed between adjacent pixels along the direction in which the gate bus lines extend. Such a drive method is referred to as “2-line dot-inversion drive (2H dot-inversion drive)”. FIG. 8 is a polarity diagram showing polarities of pixel voltage being applied to pixel formation portions on a display screen during a given frame period in a liquid crystal display device employing the 2-line dot-inversion drive. In the case of this liquid crystal display device, the polarity of the pixel voltage is inverted every two gate bus lines, and therefore power consumption and heat generation are reduced compared to the drive method in which the polarity of the pixel voltage is inverted every gate bus line.
Also, there has been proposed a liquid crystal display device employing a charge-sharing method in which short circuit is caused to occur between adjacent source bus lines for a predetermined time period from the start of each horizontal scanning period in order to further reduce power consumption. In the case of the liquid crystal display device employing the dot-inversion drive method (including the 2-line dot-inversion drive method), adjacent source bus lines are opposite in voltage polarity to each other, and furthermore, for full-white and full-gray screen display patterns, their voltage absolute values are almost equal. Accordingly, in the case of a normally-black type, short circuit between adjacent source bus lines causes voltage on each source bus line to conform with voltage corresponding to black display. Note that the voltage corresponding to black display is referred to below as “black voltage”.
However, in the case of employing the charge-sharing method for a 2-line dot-inversion drive liquid crystal display device, a stripe might be visually recognized on every line on the display screen. This will be described with reference to FIG. 9. In FIGS. 9A to 9E are signal waveform diagrams where white display is being performed in a normally-black type liquid crystal display device employing both the 2-line dot-inversion drive method and the charge-sharing method. FIGS. 9A to 9C show gate signal waveforms, FIG. 9D shows a waveform of short-circuit control signal for causing short circuit between adjacent source bus lines, and FIG. 9E shows a data signal waveform. Note that hereinafter, a horizontal scanning period in which the polarity of a data signal S(i) is inverse relative to that of one horizontal scanning period previous thereto is referred to as a “1H period”, and the next horizontal scanning period is referred to as a “2H period”. In addition, reference character Vc denotes a midpoint potential of the data signal S(i).
In the 1H period, short circuit occurs between adjacent source bus lines during a period in which the logic level of a short-circuit control signal Csh is high (hereinafter, referred to as a “charge-sharing period”). As a result, the voltage of the data signal S(i), which corresponds to white display, approximates black voltage. Note that the voltage corresponding to white display is referred to below as “white voltage”. After the charge-sharing period, the voltage of the data signal S(i) rises to white voltage. Thereafter, when the charge-sharing period starts in the 2H period, the voltage of the data signal S(i), which is white voltage, approximates black voltage.
Here, looking at the voltage of the data signal S(i) after the charge-sharing period both in the 1H and 2H periods, the voltage in the 1H period is negative, whereas the voltage in the 2H period is positive. This is because it is not possible to ensure enough time to allow the charge-sharing period to completely change the voltage of the data signal S(i) from white voltage to black voltage. Therefore, the time required for the voltage of the data signal S(i) to reach white voltage after the charge-sharing period is longer in the 1H period than in the 2H period. As a result, the charging rate for the pixel capacitance of the pixel formation portion charged in the 2H period (hereinafter, simply referred to as the “2H period charging rate”) becomes higher than the charging rate for the pixel capacitance of the pixel formation portion charged in the 1H period (hereinafter, simply referred to as the “1H period charging rate”). Thus, a line (row) with a relatively high charging rate and a line (row) with a relatively low charging rate occur alternately, and are visually recognized as stripes on the entire display screen. Note that the charging rate is represented by a proportion of voltage actually generated at the drain electrode (connected to the pixel electrode of the pixel formation portion) to voltage applied to the source bus line.
For example, Japanese Laid-Open Patent Publication Nos. 2003-337577 and 2005-156661 disclose inventions of a liquid crystal display devices in which the pulse width of the gate signal is adjusted to control the charging rate in order to eliminate such a display defect due to the above difference in the charging rate between the 1H and 2H periods. In addition, Japanese Laid-Open Patent Publication No. 2004-61590 discloses an invention of a liquid crystal display device in which conditions for the rise of drain waveforms during horizontal scanning periods are equalized by resetting a source driver output during a blanking period in each horizontal scanning period.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2003-337577
[Patent Document 2] Japanese Laid-Open Patent Publication No. 2005-156661
[Patent Document 3] Japanese Laid-Open Patent Publication No. 2004-61590